(a) Technical Field
The present invention relates to a method of forming a transistor. More particularly, the present invention relates to a method of forming a stable transistor by dual source/drain implantation.
(b) Description of the Related Art
A transistor generally includes a gate oxide layer and a gate polysilicon layer stacked together, and source and drain regions on both sides of the gate polysilicon layer. Hereinafter, a conventional method of forming a transistor will be described with reference to the accompanying drawings.
FIG. 1 and FIG. 2 are cross-sectional views showing a conventional method of forming a transistor.
Referring to FIG. 1, a gate oxide layer 12 and gate polysilicon layer 14 are formed on a silicon substrate 10. Subsequently, low energy ion implantation regions 16 are formed in substrate 10 and aligned with both sides of gate polysilicon layer 14. Pocket ion implantation regions 18 are formed below low energy ion implantation regions 16. Gate spacers 19 are formed on both sidewalls of gate polysilicon layer 14. As shown in FIG. 1, reference numeral 20 denotes columnar grains of gate polysilicon layer 14, and reference numeral 22 denotes a grain boundary of gate polysilicon layer 14.
Referring to FIG. 2, high energy ion implantation regions 26 are formed by implanting source/drain impurities 24 at a high implantation energy into an entire surface of silicon substrate 10. Gate polysilicon layer 14 and gate spacers 19 are used as an implantation mask for forming high energy ion implantation regions 26. Consequently, source and drain regions are composed of low energy ion implantation regions 16, pocket ion implantation regions 18, and high energy ion implantation regions 26.
According to the conventional method of forming a transistor, high-energy source/drain impurities 24 are ion-implanted after forming gate polysilicon layer 14. Some of impurities 24, such as fluorine, may reach a bottom of gate oxide layer 12 through grain boundary 22 between columnar grains 20 of the gate polysilicon layer 14, as denoted by reference numeral 28, and may damage silicon substrate 10, which damage may increase a leakage current and deteriorate the reliability and performance of a semiconductor device.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.